One goal in the fabrication of integrated circuitry is to produce a circuit having maximum circuit density. More succinctly, the goal is to provide more circuit capability in a smaller circuit surface area. This goal extends to the fabrication of EPROMs. An EPROM is a read only memory device in which stored data may be erased and new data written in its stead. A widely used type of EPROM is the floating gate field effect transistor type.
A partial schematic diagram of an EPROM using floating gate field effect transistors is shown in FIG. 1. Memory cells 26-1-1 through 26-2-4 are floating gate field effect transistors. Row decoder 28 provides output signals on row lines 24-1 and 24-2 in response to signals provided on row address input leads 21 and from read/write indicator 23. Column decoder 29 provides and receives signals on column lines 25-1 through 25-5 in response to signals provided on column address input leads 22 and from read/write indicator 23. A memory output signal is provided on output lead 27. A data bit stored in, for example, memory cell 26-1-1 is read by providing a high voltage output signal on row line 24-1 and providing a low voltage output signal on all other row lines. Column decoder 29 then senses, via column lines 25-1 and 25-2, the impedance of memory cell 26-1-1. If the floating gate of memory cell 26-1-1 contains excess electrons, the negative charge of these excess electrons raises the threshold voltage of memory cell 26-1-1 so that the voltage provided on row line 24-1 is insufficient to cause the channel of memory cell 26-1-1 to conduct. Therefore, column decoder 29 detects a high impedance and provides an appropriate signal on output lead 27. If there are no excess electrons stored on the floating gate of memory cell 26-1-1, then the voltage supplied on row line 24-1 is sufficient to cause memory cell 26-1-1 to conduct. Therefore, column decoder 29 detects a low impedance and provides the appropriate signal on output lead 27.
EPROM 20 is thus programmed by negatively charging the floating gate of selected memory cells. This is accomplished by injecting electrons through the insulating layer between the floating gate and the substrate of the memory cell. One fact of particular importance in understanding the present invention is the relationship between this injection and the electric field from the floating gate to the channel of a floating gate field effect transistor. The greater the field between the floating gate and the channel of the floating gate field effect transistor, the greater the injection or discharge current, depending upon the polarity of the electric field.
One prior art method for fabricating an EPROM that includes floating gate field effect transistor memory cells is described in McElroy, U.S. Pat. No. 4,373,248, entitled "Method of Making High Density Semiconductor or the Like", issued Feb. 15, 1983, and assigned to the assignee of the present invention. As shown in FIGS. 8A-8F thereof, the floating gate patterns and defines the channel area of the floating gate field effect transistor memory cells. Experimental evidence has shown that the EPROM cell of McElroy requires a voltage level of approximately 18 volts (for a floating gate to substrate insulator of silicon dioxide having a thickness of 350 angstroms and an interpoly insulator composed of 250 angstroms of silicon nitride and 250 angstroms of silicon dioxide) on the control gate (row line) to efficiently transfer charge through the insulator from the channel to the floating gate. This voltage limits the extent to which the EPROM cell of McElroy can be reduced in size because that voltage level requires certain spacing between active elements in order to avoid breakdown currents and unwanted field effects in the EPROM. Therefore, it is desirable to provide an EPROM cell which may be programmed using a minimum voltage level.
Moreover, a conventional buried diffusion which forms at least a portion of a column line 25 (see FIG. 1) may exhibit a resistance of around 30 ohms per square. This amount of resistance is typically too high for the buried diffusion alone to operate as a column line. Thus, memory arrays typically include a metallic strapping line which parallels and overlies a buried diffusion line to lower this resistance. A contact between the buried diffusion and metallic strapping line is provided for each of a predetermined number of memory cells. As a result, a column line includes a metallic strapping line electrically in parallel with a buried diffusion line, and the overall impedance of a column line greatly decreases compared to the impedance achievable with the use of only a buried diffusion line.
However, semiconductor substrate area must be dedicated to providing the contacts between the metallic strapping lines and the buried diffusion lines. This contact area lowers the memory array cell density over the density which could be achieved if some of the contact areas could instead be used for memory cells. Therefore, it is desirable to provide an EPROM cell which requires fewer contacts between buried diffusion lines and metallic strapping lines.